1 ? hc-55564/883 continuously variable slope delta-modulator (cvsd) the hc-55564/883 is a half duplex modulator/demodulator cmos intergrated circuit used to convert voice signals into serial nrz digital data and to reconvert that data into voice. the conversion is by delta-modulation, using the continuously variable slope (cvsd) method of modulation/demodulation. while the signals are compatible with other cvsd circuits, the internal design is unique. the analog loop filters have been replaced by very low power digital filters which require no external timing components. this approach allows inclusion of many desirable features which would be difficult to implement using other approaches. the fundamental advantages of delta-modulation, along with its simplicity and serial data format, provide an efficient (low data rate/low memory requirements) method for voice digitization. the device may be easily configured with the national tp3040 pcm/cvsd filter. the hc-55564/883 is usable from 9k bits/sec to above 64kbps. for more applications information, see application notes an576 and an607. features ? this circuit is processed in accordance to mil-std-883 and is fully conformant under the provisions of para- graph 1.2.1.requires few external parts ? all digital ? requires few external parts ? low power drain ? time constants determined by clock frequency; no cali- bration or drift problems: automatic offset adjustment ? half duplex operation under digital control ? filter reset under digital control ? automatic overload recovery ? automatic ?quiet? pattern generation ? agc control signal available applications ? voice transmission over data channels (modems) ? voice/data multiplexing (pair gain) ? voice encryption/scrambling ?voicemail ? audio manipulations: delay lines, time compression, echo generation/suppression, special effects, etc. ? pagers/satellites ? data acquisition systems ? voice i/o for digital systems and speech synthesis requiring small size, low weight, and ease of repro- grammability pinouts ordering information part number temperature range package hc1-55564/883 -55 o c to +125 o c 14 lead cerdip hc4-55564/883 -55 o c to +125 o c 20 lead ceramic lcc hc-55564/883 (cerdip) top view hc-55564/883 (clcc) top view v dd analog gnd a out agc a in nc nc dig out fz dig in apt enc /dec clock dig gnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 3 4 5 6 7 9101112 220 119 8 15 14 18 17 16 13 nc v dd analog gnd digital fz a out nc agc nc a in digital in nc apt nc encode /decode clock nc digital nc nc out gnd october 1999 fn3738.1 o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
2 functional diagram pin description pin no. 14 lead dip pin no. 20 lead lcc symbol description 12v dd positive supply voltage. voltage range is +3.2v to +6.0v. 2 3 analog gnd analog ground connection to d/a ladders and comparator. 34a out audio out recovered from 10-bit dac. may be used as side tone at the transmitter. presents approximately 75k ? source with dc offset of v dd /2. within 2db of audio input. should be externally ac coupled. 46agc automatic gain control output. a logic low level will appear at this output when the recovered signal ex- cursion reaches one-half of full scale value. in each half cycle full scale is v dd /2. the mark-space ratio is proportional to the average signal level. 58a in audio input to comparator. should be externally ac coupled. presents approximately 200k ? in series with v dd /2. 6, 7 1, 5, 7, 9, 10, 11, 15, 17 nc no internal connection is made to these pins. 812digital gnd logic ground. 0v reference for all logic inputs and outputs. 9 13 clock sampling rate clock. in the decode mode, must be synchronized with the digital input data such that the data is valid at the positive clock transition. in the encode mode, the digital data is clocked out on the negative going clock transition. the clock rate equals the data rate. 10 14 encode / decode a single cvsd can provide half-duplex operation. the encode or decode function is selected by the logic level applied to this input. a low level selects the encode mode, a high level the decode mode. 11 16 apt alternate plain text input. activating this input caused a digital quieting pattern to be transmitted, however; internally the cvsd is still functional and a signal is still available at the a out port. active low. 12 18 digital in input for the received digital nrz data. 13 19 fz force zero input. activating this input resets the internal logic and forces the digital output and the recov- ered audio output into the ?quieting? condition. an alternating 1-0 pattern appears at the digital output at 1/2 the clock rate. when this is decoded by a receive cvsd, a 10mv p-p inaudible signal appears at audio output. active low. 14 20 digital out output for transmitted digital nrz data. note: 1. no active input should be left in a ?floating condition?. 3-bit shift step size syllabic filter 4ms register logic digital modulator 1 signal estimate filter 1ms 10-bit dac apt (14) digital out f/f reset 6 z out 10 d t reset 10-bit dac 10 (3) a out (side tone) (4) agc out q force zero (9) digital gnd (10) enc /dec (11) (13) clock (8) (12) digital (1) v dd 3v to 6v z in analog gnd (2) (5) a in v dd 2 comparator in reset hc-55564/883
3 absolute maximum ratings thermal information voltage at any pin . . . . . . . . . . . . . . . . . . .gnd -0.3v to v dd +0.3v maximum v dd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v minimum v dd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.2v junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175 o c storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . .+300 o c esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000v thermal resistance ja jc cerdip package . . . . . . . . . . . . . . . . . . . 66 o c/w 16 o c/w ceramic lcc package . . . . . . . . . . . . . . 65 o c/w 15 o c/w package power dissipation limit at +75 o c for t j at +175 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52w ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54w package power dissipation derating factor above +75 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2w/ o c ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . . 15.4w/ o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. recommended operating conditions operating temperature range . . . . . . . . . . . . . . . -55 o c to +125 o c operating supply voltage (v dd range) . . . . . . . . . . . + 3.2v to + 6.0v table 1. dc electrical performance characteristics device tested at: v supply = +5v, fclk = 16khz, operating temperature = -55 o c t a +125 o c, unless otherwise specified. parameter symbol conditions group a subgroup temperature limits units typ max supply current i dd encode mode: a in = 0v 1 +25 o c-1.5ma 2, 3 +125 o c, -55 o c- 1.5ma logic input high (note 2) v ih input level: ?1? = +3.5v, ?0? = +1.5v 1+25 o c3.5-v 2, 3 +125 o c, -55 o c3.5 - v logic input low (note 2) v il input level: ?1? = +3.5v, ?0? = +1.5v 1+25 o c-1.5v 2, 3 +125 o c, -55 o c- 1.5v logic output high (note 3) v oh i load = -40 a1+25 o c4.0-v 2, 3 +125 o c, -55 o c4.0 - v logic output low (note 3) v ol i load = +0.8ma 1 +25 o c-0.4v 2, 3 +125 o c, -55 o c- 0.4v quieting pattern amplitude (note 8) v qp fz = 0; clock inputs switched statically 1+25 o c-14mv p-p 2, 3 +125 o c, -55 o c- 14mv p-p agc threshold (note 9) v ath encode mode 1 +25 o c 0.45 0.65 f.s. 2, 3 +125 o c, -55 o c 0.45 0.65 f.s. table 2. ac electrical performance characteristics table 2 intentionally left blank. table 3. electricl performance characteristics devices characterized at: v dd = +5.0v, t a = +25 o c, operating temperature, fclk = 16khz clock sampling rate. enc /ddc = enc = encode mode, unless otherwise specified. parameter symbol conditions note temperature limits units typ max sampling rate clk a in = 0.775 v rms at 20hz 1, 12 +25 o c964kbs +125 o c, -55 o c964kbs clk duty cycle a in = 0.775 v rms at 100hz 12 +25 o c3070% +125 o c, -55 o c3070% hc-55564/883
4 audio input voltage a in a in = 100hz 4, 12 +25 o c-1.2v rms +125 o c, -55 o c-1.2v rms audio output voltage a out a in = 100hz 5, 12 +25 o c-1.2v rms +125 o c, -55 o c-1.2v rms input impedance z in a in = 100hz 6, 12 +25 o c150500k ? +125 o c, -55 o c150500k ? output impedance z out a in = 100hz 6, 12 +25 o c3525k ? +125 o c, -55 o c3525k ? transfer gain a e-d a in = 0.775 v rms at 100hz 11, 12 +25 o c-2+2db -55 o c, +125 o c-2+2db resolution res a in at 100hz. note 8 12, 13 +25 o c0.3-% of supply min step size mss 7, 12 +25 o c 0.10 0.14 % of supply clamping threshold v cth 10, 12 +25 o c 0.70 0.90 f.s. notes: 1. there is one nrz (non-return zero) data bit per clock period. data is clocked out on the negative clock edge. data is clocked into the cvsd on the positive going edge (see figure 2). clock may be run at less than 9kbps. 2. logic inputs are cmos compatible at supply voltage and are diode protected. digital data input is nrz at clock rate. 3. logic outputs are cmos compatible at supply voltage and will withstand short-circuits to v dd or ground; however, the short circuit duty cycle must not exceed 5% in order to maintain an acceptable current density level. digital data output is nrz and changes with negati ve clock tran- sitions. each output will drive one ls ttl loads. 4. recommended voice input range for best voice performance. should be externally ac coupled. 5. may be used for side-tone in encode mode. should be externally ac coupled. 6. presents series impedance with audio signal. zero signal reference is approximately v dd /2. varies with audio input level by 2db. 7. the minimum audio output voltage change that can be produced by the internal dac. 8. the ?quieting? pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions. 9. a logic ?0? will appear at the agc output pin when the recovered signal reaches one-half of full-scale value (positive or neg ative), i.e. at v dd /2 25% of v dd . 10. the recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarter s of full-scale val- ue, and will unclamp when it falls below this value (positive or negative). 11. no load condition measured from audio in to audio out. 12. the parameters listed in this table are controlled via design or process parameters and are not directly tested. these param eters are charac- terized upon initial design release and upon design changes which would affect these characteristics. 13. the minimum audio input voltage above which encoding is guaranteed to take place. table 4. electrical test requirements mil-std-883 test requirements subgroups (see table 1) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1 (note 1), 2, 3 group a test requirements 1, 2, 3 groups c and d endpoints 1 note: 1. pda applies to subgroup 1 only. table 3. electricl performance characteristics (continued) devices characterized at: v dd = +5.0v, t a = +25 o c, operating temperature, fclk = 16khz clock sampling rate. enc /ddc = enc = encode mode, unless otherwise specified. (continued) parameter symbol conditions note temperature limits units typ max hc-55564/883
5 die characteristics die dimensions: 82 x 147 x 20 1 mils metallization: type: alsi thickness: 10k? 1k? glassivation: type: silane, 3% phosphorous thickness: 13k? 2.6k? worst case current density: 2.0 x 105a/cm2 transistor count: 1896 process: cmos; saji metallization mask layout hc-55564/883 a out analog v dd digital fz digital in apt enc /dec clock a in agc out gnd digital gnd hc-55564/883
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